RTL Design Engineer

Samsung Electronics

Position Summary


With a wide range of industry-leading semiconductor solutions, we’re enabling innovative growth in markets segments from hyperscale data centers and automotive to IoT, mobile and consumer electronics.

SSIR is one of the largest R&D center outside Korea and a microcosm for Samsung Semiconductors. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and also conduct research in new and emerging areas of technology. We take pride in our ability to work on the futuristic technologies as innovation and creativity is highly valued at SSIR. We strive towards providing high reliability; high performance and value added services that enables Samsung Semiconductors to deliver world class products.

What we offer

Samsung is a global leader in technology, opening new possibilities for people everywhere. In our center you will be part of a dynamic team, in an international work environment. Being one of the best in the industry comes with hard work, but we also make it rewarding through:

Best in the industry compensation
Free breakfasts and lunches in our office
Flexible working hours/ Hybrid work environment
Transport facilities
Health & wellbeing: wellness program, e.g. subsidized gym subscription
Quarterly team events and various team activities
Learning and Development opportunities

Role and Responsibilities


Experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripherial/CPU/GPU Subsystem or other Mobile SoC Subsystem.
Understanding of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI and AHB.
Creating micro-architecture and detailed design documents for SoC Subsystem design keeping in mind performance, power, area requirements.
Strong debugging skills and very good experience in DV tools like Verdi, NCSIM.
SOC Integration experience preferred of Top Level, Block Level or Subsystem level.
Working with DV team to enable verification coverage improvement. Working on GLS closure with DV, PD and Modelling team.
Must have knowledge in clock domain crossing (CDC), Linting, UPF, DFT and Multi-Voltage-Rule-Check analysis.
Understanding on ASIC Synthesis, and static timing reports analysis, Formal checking, etc. is a must.
Understanding and defining constraints and critical high speed path timing closure working with back end teams.
Skills and Qualifications









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